RF Frequency Synthesis

In a fractional-N synthesis PLL, the periodic pulse removal in the feedback chain necessary to synthesise an exact frequency gives a high level of pattern jitter at the phase detector. resulting in regular jitter components (spurs) in the VCO output.  These spurious components define the carrier-to-spurious ratio (CSR) of the synthesised signal, which is a key factor in selecting a synthesiser PLL for RF applications. Normally, the only way of improving the CSR is to use a lower bandwidth in the loop filter.

The two disadvantages of low loop filter bandwidth are

• A larger capacitor size (a bigger silicon area, or perhaps even a requirement for an extra off-chip capacitor). This leads to increased cost.
• an increased settling time. This leads to slower channel switching.

Putting an AJC in the divider chain, after the pulse removal stage, reduces the jitter presented to the phase detector. This allows the designer to specify a larger-bandwidth filter, thus reducing capacitor size and improving frequency agility.

Key benefits

• Reduces product cost by allowing fully-integrated PLL (no off-chip passives) with reduced loop filter requirement.
• For FSK / PSK modulated PLLs, this increases the modulation bandwidth, permitting a higher data rate.
• Smaller overall footprint for the PLL, reducing cost and design time.
• Settling time reduced: faster channel search, faster frequency hopping.