Low Power PLL

Use of the Toric AJC as a post-VCO clean-up stage redefines the power/performance/area tradeoffs faced by the chip architect.

The most prominent benefit is in eliminating tuned-circuit (LC-tank) VCOs. These are typically characterised by high current consumption, large footprint for integrated inductor, and narrow tuning range, but these are the only choice where low jitter is needed.

Smaller and lower-power ring oscillators normally generate a higher level of jitter. However, the jitter can now be reduced to the required level using an AJC as a clean-up stage.  The combined structure has a lower power and smaller footprint than an LC-tank VCO with similar performance.

Deployment of an AJC also brings a considerable design-cycle benefit: the performance of the ring-oscillator/AJC combination is easier to simulate accurately than the LC version, whose inductor is sensitive to local layout and is influenced by other metal layers. The result is a right-first-time design.

Key benefits

• Lower total power.
• More reliable convergence with simulation, fewer design iterations.
• Wider tuning range, eliminates banked inductor/capacitors in wide range PLLs.
• Shorter design time.