Phase Filter
PhaseFilter is a set of reference designs embodying AJC technology, optimised for rapid design-in and optimal performance.
PhaseFilter was created to give designers a short cut to resolving internal jitter problems on ICs, enabling IC vendors to create a range of area-efficient, low-power, high-performance clock processing macros.
PhaseFilter uses generic circuit elements, making it suitable for a wide range of semiconductor processes and geometries. On a typical CMOS process, with a 2:1 operating range in the GHz region, a far-from-carrier phase noise density of -150dBc/Hz is possible, making it suitable for a wide variety of jitter-sensitive applications.
PhaseFilter is also suitable as a preventative fix, in re-worked designs where jitter performance is critical.
Key Benefits – PhaseFilter
PhaseFilter provides a cure for internal jitter problems on complex chips with:
- significantly lower power and area overhead than equivalent PLL-based solutions
- minimalist design requirements which are easy to simulate and verify
- better system tolerance to low power (higher jitter) clock sources.
For more information:
Design Flow
PhaseFilter is a low noise clock filter designed for interfacing system clocks to jitter-sensitive circuit functions.
An all-analogue design, PhaseFilter is optimised for minimum area and power.
By employing a non-VCO retiming method, PhaseFilter avoids the classic drawbacks of tuned-circuit PLLs: power consumption, chip area and physical layout sensitivity.
Delivered as a scaleable reference design based on a 180nm generic CMOS, PhaseFilter is highly portable over a wide range of processes, geometries and operating frequencies.
The PhaseFilter package enables designers to work at source level, tuning the design according to a full set of implementation rules.
PhaseFilter is delivered as a transparent, open-source design with simple configuration of operating frequency according to design rules. Other parameters, such as jitter bandwidth, may be fine-tuned for special cases. The design kit documentation also provides sufficient background information, at theoretical and practical level, for an experienced analogue designer to customise the design for particular power/area/performance trade-offs.
The complete reference circuit is based on Toric’s AJC (ant-jitter cell) technology, an inherently stable and process-tolerant design which functions over multiple nodes and process/voltage/temperature corners. There are no precision elements, inductors, delay lines or other layout-sensitive parts. Only transistors, resistors and capacitors are needed, making it adaptable to virtually any analogue process.
Test chips using AJC technology have been built on standard and proprietary analogue CMOS and BiCMOS processes, on geometries from 350nm down to 90nm.