Toric’s patent portfolio
Toric owns the following four patent families:
“Auto NRC”
This patent teaches the basis for Toric’s entire range of AJCs and also some variants, such as the double-divide configuration.
“Pulse insert”
This patent principally addresses clock jitter suppression and ‘skew’ removal, which is a major speed restriction in large integrated circuits. It also teaches means for extracting and restoring a clock from a digital data stream that has no associated clock, or one having excessive jitter. The following are the four principal aspects of this invention:
- pulse doubler – this provides a means for inserting missing pulses, giving a clock restoration capability.
- pulse deleter – this allows the deletion of spurious pulses, which also helps with clock restoration.
- multiphase output, dual comparator / latch output – these have applicability in many digital systems incorporating multiphase clocks. The dual comparator / latch output is an alternative to the monostable output.
- fractional-n synthesiser – AJCs can be used to reduce noise in many sorts of synthesizer, of which the most important is the fractional-n type.
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“Adiabatic AJC”
This patent teaches the ‘adiabatic’ principle: a simplified core of the AJC is powered from the signal input.
In comparison with the AJC described in ‘Auto NRC’, the simplified core can operate at higher frequencies with less power consumption. Variants are also described, including one where standard digital logic is used in place of the differential comparator, an arrangement which gives advantages in speed, simplicity and power consumption.
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“EF AJC”
This patent application teaches that the original (and adiabatic) core AJCs are improved by use of a feedback loop providing feed-forward cancellation. This provides two principal advantages: it extends the lowest suppression frequency at least tenfold; and it improves AJC suppression, typically by up to 20dB or more at mid-range sideband frequencies. Together, compared with the configuration described in ‘Auto NRC’ and ‘Adiabatic AJC’, these improve the reduction of ‘total time jitter’, typically doubling jitter reduction when expressed in dB. A further advantage is that the feedback loop allows the core AJC to be designed for optimal reduction of cycle-to-cycle jitter without regard to noise reduction at mid-to-low-range sideband frequencies, which allows the feedback loop to be operated at higher feedback gain and so improves the overall performance of the AJC.