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A proliferation of PLLs

 

A complex SoC typically consists of a large number of linked building-blocks, including one or more processors.  Each of these blocks may require a unique clock source, supplied by a separate PLL.  In some cases, up to 20 independent PLLs may exist on a single chip. 

 

Some examples of physical blocks requiring dedicated clock or frequency sources are:

 

Each of these clock generators consumes silicon area, and supply current, in proportion to the purity of the clock.

 

MULTIPLE CLOCK GENERATOR (MCG)

 

Toric's MCG is a versatile multi-clock generator with GHz capability, targeting complex SoC .

Its innovative approach to on-chip clock generation and control offers considerable system, power and area benefits over conventional PLL-based designs.

 

BENEFITS:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LOW POWER OPERATION

MCG offers considerable savings in power and cost compared to the multiple independent PLLs on a large SoC (see right), by using a highly efficient common clock-generation engine.

 

MCG consists of a central digital frequency generator (shown in yellow) with up to 256 programmable clock driver channels, each feeding an analogue processing stage (shown in blue) which controls the clock jitter and skew. Jitter is suppressed using Toric's PhaseFilter topology.

 

Each of these analogue stages can be placed at an optimal location on the IC; either next to the digital block, or adjacent to the circuit being clocked. An advantage of the latter option is that additional jitter accumlated in the clock routing path can be suppressed.

 

The MCG's frequency synthesiser can be driven by a single master clock source, whose frequency must be higher than the greatest clock frequency required. A basic low-power PLL can be used, since is jitter requirement is not critical.

 

 

PROGRAMMABLE FEATURES

Digital synthesis in combination with Toric's new technology allows precise control of clock generation. Dynamic control and gating of clock frequency is possible without the latency overhead associated with PLLs. MCG's control features include:

 

 

Register access is via AMBA APB or a generic bus interface, allowing easy integration with most embedded processors.

 

 

MCG FACILITATES CHIP POWER MANAGEMENT
Dynamic Voltage-Frequency Scaling (DVFS) and power-gating are widely used for power-sensitive IC applications, especially embedded processors and battery-powered devices. Until now, however, these techniques could not be used in clock generators and PLLs.  Generally, they are kept powered-up and running because of the long stablisation time required immediately following a power-up or frequency change.

A major advantage of MCG is that the clock is available in a few cycles after power-up, and maintains timing integrity over a frequency change.  There is none of the ‘out-of-lock’ behaviour associated with PLLs. This gives the programmer the opportunity to use power-gating and clock throttling more aggressively, without the restrictions typically imposed by PLL hardware, leading to improved net energy efficiency.

 

For more information : MCG Product Brief acro

 

DELIVERY


MCG will be available in 2008 as a design kit as follows:

 

 

Intermediate releases of MCG will be available for evaluation and for licensing into customers' own designs.