About Jitter

 

Where designers are hitting the jitter barrier

Jitter is the unwanted misplacement of an event in time. Any regular process is subject to jitter, from the sub-atomic processes in a caesium clock, to the arrival of trains at a station. In IC design, there are three principal areas where the problem of jitter continues to occupy the time and resources of chip design teams.  In every case, the problems of jitter are being compounded by steadily rising clock speeds and falling timing margins.

 

Clock-Data jitter:  the sychronisation cliff edge

Consider the challenge: a gigabit data stream, appearing as a noise-like signal, must be sampled to a timing resolution of a few picoseconds. The sampling reference must be estimated from the data itself via a PLL. Any extra jitter on the PLL will cause the data to be sampled at the wrong instant, giving data errors.

 

Studies have shown that a 10% increase of jitter on a clock recovery circuit can lead to a bit-error rate increase of 3 orders of magnitude: the cliff-edge effect. 
Managing and controlling clock jitter is therefore a major concern for designers of serial data communications chips, where jitter performance is a key specification item.

 

ADC Sampling jitter: right value, wrong time

The advent of digital baseband processing in mass-market digital radio standards, such as WiFi, Bluetooth and GSM, calls for A/D converters with wide dynamic range and sampling speeds in excess of 100Ms/s. A simple calculation shows that any error in the sampling clock translates directly into equivalent sampled noise.

Manufacturers of high-resolution RF ADCs have realised a painful fact: although they may have designed a perfect product, their customers are struggling to get enough bits of resolution out of the converters, simply because they cannot provide a sampling clock with low enough jitter.

 

Synthesis jitter: outside the mask

Today’s RF protocols rely on closely spaced radio channels with carefully controlled levels of adjacent channel interference. Standard masks define how the transmitter’s energy must be confined to a narrow frequency band. Due to exact channel placement requirements, the only practical method of designing such a transmitter is with a synthesized RF generator, with precision control of frequency.

Tighter packing of channels led designers in the 1980s to develop fractional-N synthesisers, where the frequency could be set at any arbitrary value. This technique relies on adding a deliberate amount of short-term frequency variation to achieve a required average frequency. This jitter, which is useful in generating a precise frequency, is also an unwanted spectral component of the PLL’s output.

 

Modern synthesiser designs, based on the PLL principle, are designed to eliminate the spurious out-of-band frequency components, but at the expense of large on-chip or off-chip filter components, and restricting the agility with which the PLL can jump to new frequency.