“EF AJC”
Abstract
An anti-jitter circuit for reducing time jitter in an input pulse train comprises an integrator, a DC removal circuit and a comparator. The anti-jitter circuit also has a feedback loop effective to suppress phase deviation of the output pulse train in response to jitter.
Commentary
This patent application teaches that the original (and adiabatic) core AJCs are improved by use of a feedback loop providing feed-forward cancellation. This provides two principle advantages: it extends the lowest suppression frequency at least tenfold; and it improves AJC suppression, typically by up to 20db or more at mid-range sideband frequencies. Together, compared with the configuration described in ‘Auto NRC’ and ‘Adiabatic AJC’, these improve the reduction of ‘total time jitter’, typically doubling jitter reduction when expressed as dBs. A further advantage is that the feedback loop allows the core AJC to be designed for optimal reduction of cycle-to-cycle jitter without regard to noise reduction at mid-to-low-range sideband frequencies which allows the EF loop to be operated at higher feedback gain and so improve the overall performance of the AJC.
PCT filing
Filed on 21st July 2005 as PCT/GB2005/002864 with a priority date of 26th July 2004.