Clock Tree: Quiet Nodes

On a large IC containing embedded processors, interfaces, memory and analogue building blocks, the clock tree can consume as much as 25% of the chip current.

Many standard PLL IPs provided for ASIC integration, offer low power and small silicon area at the expense of jitter. This makes it difficult to integrate jitter-sensitive blocks. Also, in signal processing applications, including RF, automotive and multimedia, ADCs and DACs are integrated with digital blocks, but require a higher level of clock purity than these blocks.

An upgrade of the entire clock generation system would typically result in an increase in supply current and footprint.  An alternative course is to incorporate localised AJC-based clock filtering stages where needed.

Where individual blocks exhibit jitter-related problems in debug, an AJC stage can be added as a fix, as an alternative to a major redesign of the entire clocking subsystem.

Key benefits

• Allows clocking problems to be addressed by a clean-up stage, rather than redesign of the clock tree.
• Allows the designer to achieve an optimal power/performance balance for the clock tree in mixed-signal designs.
• Faster resolution of unforeseen jitter-related bugs.
• Highly versatile, process and technology independent.