Overview of Toric’s AJC technology
Toric’s AJC (Anti-Jitter Cell) technology provides IC designers, semiconductor IP authors and system integrators with a radically new approach to clock jitter management. An embedded AJC:
- tackles jitter right at the most critical parts of a chip
- requires no signals other than clock input and power
- requires no external off-chip components.
Toric’s AJC is quite different from conventional PLLs. It has no VCO, instead using a novel form of feedforward correction requiring very few components. It is a generic circuit topology realisable in a wide-range of semiconductor technologies and geometries. Its minimalist approach makes it a secure choice for projects with tight area and power budgets.
How AJC technology works
Toric’s AJC technology uses standard analogue components: charge pump, capacitor, current sink, comparator, and RC filter components.
These operate in four stages:
- Each active rising (or falling) edge of the incoming clock is first converted into a fixed-charge current pulse which is dumped into a balanced integrator, so that phase errors are converted into voltage offsets on a cycle-by-cycle basis.
- The integrator is dc-stabilised using a current feedback loop. The time constant of the loop also programmes the jitter bandwidth
- A reverse process, converting voltage offset into an opposite phase correction, removes the timing error from each pulse of the clock signal.
This animation shows how the de-jittered waveform is generated:
Each stage can be implemented using standard, well-characterised analogue building blocks, chosen from a designer’s own IP library or created specifically for the AJC. No off-chip components are needed.
For more information on the theory of AJC operation:
For a list of papers and patents: