“Adiabatic AJC”
Abstract
A phase noise reduction circuit for reducing phase noise in an input pulse train consisting of pulses which are all of the same length and which, in the absence of phase noise, have a nominal frequency f, includes a DC removal circuit for removing a DC level from the input pulse train, or integrator for integrating the input pulse train after a DC level has been removed therefrom by the DC removal circuit and a comparator for deriving from the integrated pulse train an output pulse train containing periodic transitions at half said nominal frequency, ½ f. The input pulse train may be derived using a monostable circuit.
Commentary
This application teaches the ‘adiabatic’ principle: a simplified core of the AJC is powered from the signal input.
In comparison with the AJC described in ‘Auto NRC’, the simplified core can operate at higher frequencies with less power consumption. Variants are also described, including one where standard digital logic is used in place of the differential comparator, an arrangement which gives advantages in speed , simplicity and power consumption.
PCT filing
Filed on 12th November 1999 as PCT application PCT/GB99/03776 with priority dates 13 November 1998 and 1st April 1999.